The present invention relates to a semiconductor testing device in which the arrangement of bonding pads on a chip is modified, and in correspondence to this modification, the construction of a probe card and the arrangement of chips on a wafer are modified so that a plurality of chips on the wafer can be tested simultaneously.
Heretofore, a semiconductor testing device as shown in FIG. 1 was used to test semiconductor memory chips in the form of a wafer, hereinafter referred to as "wafer testing" or "wafer test" when applicable. As shown in FIG. 1, a probe card 3 for semiconductor devices, hereinafter referred to as "chips" when applicable, on a wafer 2 to be tested is fixed to a prober 1 and the wafer is positioned accurately on a prober stage 7. The probe card 3 is provided with probes 4 formed as an elongated conductor in correspondence to bonding pads formed on a chip to be tested so that, when the probes 4 are placed in contact with the bonding pads, a tester 5 and the chip 2 are connected in an electrical circuit. The tester 5 operates to deliver various signals to the chip 2 and to sense and evaluate the output data from the chip 2 thereby to carry out wafer testing. In the case when the chip 2 is found to be unsatisfactory as a result of such testing, a mark is printed on the chip 2 by an inker 6 on the prober 1 so that satisfactory chips can be distinguished from unsatisfactory chips. In testing all of the chips on a wafer, the wafer is usually moved in increments by the length or width of a chip. In other words, upon completion of the testing of each chip, the wafer is moved in a lengthwise or widthwise direction by as much as the size of the chip. When a row of chips arranged in a longitudinal or lateral direction have been tested, the following row of chips is tested. The chips, and accordingly the wafer, are moved with the sensor of the probe card operated over the wafer and a fully automatic movement system is provided which automatically operates the prober In FIG. 1, reference numeral 8 designates a microscope for observing the testing operations.
The probe cards 3 are each adapted for use with the particular type of chips to be tested. An example of a probe card 3 is shown in FIG. 2. In FIG. 2, reference numeral 3 designates the probe card. The probe card 3 is rectangular or circular or shaped as needed as that it can be readily coupled to the tester. The probe card 3 has a central window 3a so that the probes 4 of the probe card 3 can be correctly aligned with the chips 2 to be tested through the window 3a. The probes 4 are arranged on the probe card 3 with connections made to the tester. The number of probes 4 provided is determined from the number of bonding pads 2a on the chip 2, the distance between adjacent probes 4, and the size of the window 3a.
With the conventional wafer testing device constructed as described above, the chips on a wafer can be tested only one at a time. Accordingly, in testing large-capacity semiconductor memories or the like, the time required for testing each device is great and becomes more so as the memory capacity is increased. Thus, the conventional wafer test device is disadvantageous in that the test time required is relatively long.